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cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-00856 rev. *g revised june 07, 2017 S29JL064J 64-mbit (8m 8-bit/4m 16-bit), 3 v, simultaneous read/write flash distinctive characteristics architectural advantages ? simultaneous read/write operations ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency between read and write operations ? flexible bank architecture ? read may occur in any of the three banks not being programmed or erased ? four banks may be grouped by cu stomer to achieve desired bank divisions ? boot sectors ? top and bottom boot sectors in the same device ? any combination of sectors can be erased ? manufactured on 0.11 m process technology ? secured silicon region: extra 256-byte sector ? factory locked and identifiable: 16 bytes available for secure, random factory electronic serial number; verifiable as factory locked through autoselect function ? customer lockable: one-time programmable only. once locked, data cannot be changed ? zero power operation ? sophisticated power management circuits reduce power consumed during inactive periods to nearly zero ? compatible with jedec standards ? pinout and software compatible with single-power-supply flash standard package options ? 48-ball fine-pitch bga ? 48-pin tsop performance characteristics ? high performance ? access time as fast as 55 ns ? program time: 7 s/word typical using accelerated programming function ? ultra low power consumption (typical values) ? 2 ma active read current at 1 mhz ? 10 ma active read current at 5 mhz ? 200 na in standby or automatic sleep mode ? cycling endurance: 1 million cy cles per sector typical ? data retention: 20 years typical software features ? supports common flash memory interface (cfi) ? erase suspend/erase resume ? suspends erase operations to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ? data# polling and toggle bits ? provides a software method of detecting the status of program or erase operations ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences hardware features ? ready/busy# output (ry/by#) ? hardware method for detecting program or erase cycle completion ? hardware reset pin (reset#) ? hardware method of resetting the internal state machine to the read mode ? wp#/acc input pin ? write protect (wp#) function protects sectors 0, 1, 140, and 141, regardless of sector protect status ? acceleration (acc) function accelerates program timing ? sector protection ? hardware method to prevent any program or erase operation within a sector ? temporary sector unprotect allo ws changing data in protected sectors in-system general description the S29JL064J is a 64 mbit, 3.0 volt-only fl ash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. word mode data appears on dq15?dq0; byte mode data appears on dq7?dq0. the device is designed to be programmed in-system with the standard 3.0 volt v cc supply, and can also be programmed in standard eprom programmers. the device is available with an access time of 55, 60, 70 ns and is of fered in a 48-ball fbga or 48-p in tsop package. standard contr ol pins?chip enable (ce#), write enable (we#), and output enable (oe#)?control normal read and write operations, and avoid bus contention issues. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provided fo r the program and erase operations.
document number: 002-00856 rev. *g page 2 of 60 S29JL064J contents distinctive characteristics .................................................. 1 general description ............................................................. 1 1. simultaneous read/write operations with zero laten- cy ....................................................................................... 3 1.1 S29JL064J features...................................................... 3 2. product selector guide ............................................... 4 3. block diagram .............................................................. 4 4. connection diagrams .................................................. 5 4.1 48-pin tsop package ................................................... 5 4.2 48-ball fbga package .................................................. 6 5. pin description ............................................................. 6 6. logic symbol ............................................................... 7 7. ordering information ................................................... 8 8. device bus operations .............................................. 10 8.1 word/byte configuration.............................................. 10 8.2 requirements for reading array data......................... 11 8.3 writing commands/command sequences.................. 11 8.4 simultaneous read/ write operations with zero latency......................................................... 11 8.5 standby mode.............................................................. 12 8.6 automatic sleep mode................................................. 12 8.7 reset#: hardware reset pin............. .............. .......... 12 8.8 output disable mode ................................................... 13 8.9 autoselect mode .......................................................... 17 8.10 boot sector/sector block protection and unprotection.......................................................... 18 8.11 write protect (wp#) ..................................................... 19 8.12 temporary sector unprotect........................................ 20 8.13 secured silicon region....... ............ ........... ........... ....... 22 8.14 hardware data protection............................................ 23 9. common flash memory interface (cfi) ................... 24 10. command definitions ................................................ 27 10.1 reading array data ..................................................... 27 10.2 reset command .......................................................... 27 10.3 autoselect command sequence ................................. 28 10.4 enter secured silicon region/exit secured silicon region command sequence............. 28 10.5 byte/word program comman d sequence...... ............. 28 10.6 chip erase command sequen ce ........... .............. ....... 30 10.7 sector erase command sequence ............................. 30 10.8 erase suspend/erase resume commands ... ............. 31 11. write operation status .............................................. 33 11.1 dq7: data# polling ...................................................... 33 11.2 ry/by#: ready/busy#........... .............. .............. .......... 34 11.3 dq6: toggle bit i ......................................................... 35 11.4 dq2: toggle bit ii ........................................................ 36 11.5 reading toggle bits dq6/dq2.................................... 37 11.6 dq5: exceeded timing limits ............. .............. .......... 37 11.7 dq3: sector erase timer............................................. 37 12. absolute maximum ratings ....................................... 38 13. operating ranges ....................................................... 39 14. dc characteristics ...................................................... 39 14.1 cmos compatible ........................................................ 39 14.2 zero-power flash ................. ........................................ 40 15. test conditions ........................................................... 41 16. key to switching waveforms .................................... 42 17. ac characteristics ...................................................... 43 17.1 read-only operations .......... ........... ........... ........... ....... 43 17.2 hardware reset (reset#)..... ............... .............. ......... 44 17.3 word/byte configuration (byt e#) ................................ 45 17.4 erase and program operations .................................... 46 17.5 temporary sector unprotect.. ....................................... 50 17.6 alternate ce# controlled erase and program operations............................................... 51 18. erase and programming performance ..................... 53 19. pin capacitance .......................................................... 53 20. physical dimensions .................................................. 54 20.1 ts 048?48-pin standard tsop ............. .............. ....... 54 20.2 vbk048?48-pin fbga ............. .............. .............. ....... 55 21. revision history .......................................................... 56
document number: 002-00856 rev. *g page 3 of 60 S29JL064J 1. simultaneous read/write oper ations with zero latency the simultaneous read/write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 mb banks with small and large sectors, and two 24 mb banks of large sectors. sector addresses are fixed, system software can be used to form user-defined bank groups. during an erase/program operation, any of the three non-busy b anks may be read from. note that only two banks can operate simultaneously. the device can improve overall system perform ance by allowing a host system to program or erase in one bank, then immediately an d simultaneously read from the other bank, with zero latency. this rele ases the system from waiting for the completion of program or erase operations. the S29JL064J is organized as a dual boot device with both top and bottom boot sectors. 1.1 S29JL064J features the secured silicon region is an extra 256 byte sector capable of being perm anently locked by spansion or customers. the secured silicon customer indicator bit (dq6) is permanently set to 1 if the part has been custom er locked, and permanently set to 0 if the part has been factory locked. this way, customer lock able parts can never be used to replace a factory locked part. factory locked parts provide several options. the secured silicon region may store a secure, random 16 byte esn (electronic serial number), customer code (programmed through spansion programming services), or both . customer lockable parts may utilize the secured silicon region as bonus space, reading and wr iting like any other flash sector , or may permanently lock the ir own code there. the device offers complete compatibility with the jedec 42.4 single-power-supply flash command set standard . commands are written to the command register using standard microprocessor write timings. reading data out of the device is similar to r eading from other flash or eprom devices. the host system can detect whether a program or er ase operation is complete by using the device status bits: ry/by# pin, dq7 (data# polling) and dq6/dq2 (toggle bits). after a program or erase cycle has been completed, the device automatically returns to the read mode. the sector erase architecture allows memory sectors to be erased and reprog rammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhi bits write operations during power transitions. the hardware sector protection feature disables both program and erase oper ations in any combination of the sectors of memory. this can be achieved in-s ystem or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not sele cted for erasure. true background erase can thus be achieved. if a read is needed f rom the secured silicon region (one time pr omgram area) after an erase suspend, t hen the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features . when addresses have been stable for a s pecified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both modes. bank mbits sector sizes bank 1 8 mb eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword bank 2 24 mb forty-eight 64 kbyte/32 kword bank 3 24 mb forty-eight 64 kbyte/32 kword bank 4 8 mb eight 8 kbyte/4 kword, fifteen 64 kbyte/32 kword
document number: 002-00856 rev. *g page 4 of 60 S29JL064J 2. product selector guide 3. block diagram part number S29JL064J speed option standard voltage range: v cc = 2.7?3.6v 55 60 70 max access time (ns), t acc 55 60 70 ce# access (ns), t ce 55 60 70 oe# access (ns), t oe 25 25 30 v cc v ss bank 1 address bank 2 address a21?a0 reset# we# ce# byte# dq0?dq15 wp#/acc state control & command register ry/by# bank 1 x-decoder oe# byte# dq15?dq0 status control a21?a0 a21?a0 a21?a0 a21?a0 dq15?dq0 dq15?dq0 dq15?dq0 dq15?dq0 mux mux mux bank 2 x-decoder y-gate bank 3 x-decoder bank 4 x-decoder y-gate bank 3 address bank 4 address
document number: 002-00856 rev. *g page 5 of 60 S29JL064J 4. connection diagrams 4.1 48-pin tsop package figure 4.1 48-pin standard tsop 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10
document number: 002-00856 rev. *g page 6 of 60 S29JL064J 4.2 48-ball fbga package figure 4.2 48-ball fbga 5. pin description a21?a0 22 address pins dq14?dq0 15 data inputs/outputs (x16-only devices) dq15/a-1 dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# chip enable, active low oe# output enable, active low we# write enable, active low wp#/acc hardware write protect/acceleration pin reset# hardware reset pin, active low byte# selects 8-bit or 16-bit mode, active low ry/by# ready/busy output, active low v cc 3.0 volt-only single power supply (see product selector guide on page 4 for speed options and voltage supply tolerances) v ss device ground nc not connected. no device internal signal is connected to the package connector nor is there any future plan to use the connector for a signal. the connection may safely be used for routing space for a signal on a printed circuit board (pcb). dnu do not use. a device internal signal may be connected to the package connector. the connection may be used by spansion for test or other purposes and is not intended for connection to any host system signal. any dnu signal related function will be inacti ve when the signal is at v il . the signal has an internal pull-down resistor and may be left unconnected in the host system or may be tied to v ss . do not use these connections for pcb signal routing channels. do not connect any host system signal to these connections. rfu reserved for future use. no device internal signal is currently connected to the package connector but there is potential future use for the connector for a signal. it is recommended to not use rfu connectors for pcb routing channels so that the pcb may take advantage of futu re enhanced features in compatible footprint devices. b3 c3 d3 e3 f3 g3 h3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 v ss dq15/a-1 byte# a16 a15 a14 a12 dq6 dq13 dq14 dq7 a11 a10 a8 dq4 v cc dq12 dq5 a19 a21 reset# dq3 dq11 dq10 dq2 a20 a18 wp#/acc a3 a4 a5 a6 a13 a9 we# ry/by# b2 c2 d2 e2 f2 g2 h2 dq1 dq9 dq8 dq0 a5 a6 a17 a2 a7 b1 c1 d1 e1 f1 g1 h1 v ss oe# ce# a0 a1 a2 a4 a1 a3
document number: 002-00856 rev. *g page 7 of 60 S29JL064J 6. logic symbol 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# byte# ry/by# wp#/acc
document number: 002-00856 rev. *g page 8 of 60 S29JL064J 7. ordering information the order number is formed by a valid combination of the following: valid combinations ? standard note: 1. packing type 0 is standard. specify other options as required. S29JL064J 55 t f i 00 0 packing type 0=tray 3 = 13-inch tape and reel model number (additional ordering options) 00 = standard configuration temperature range i = industrial (?40c to +85c) a = automotive, aec-q100 grade 3 (-40c to +85c) package material set f = pb-free h = low-halogen, pb-free package type b = fine-pitch ball grid array (fbga) package t = thin small outline package (tsop) standard pinout speed option 55 = 55 ns 60 = 60 ns 70 = 70 ns product family S29JL064J: 3.0 volt-only, 64 mbit (4 m x 16-bit/8 m x 8-bit) simultaneous read/ write flash memory manufactured on 110 nm process technology S29JL064J valid combinations device number/ description speed (ns) package type & material temperature range model number packing type package description S29JL064J 55, 60, 70 tf i000, 3 (1) ts048 tsop bh vbk048 fbga
document number: 002-00856 rev. *g page 9 of 60 S29JL064J valid combinations ? au tomotive grade / aec-q100 the table below lists configurations that are automotive grade / aec-q100 qualified and are planned to be available in volume. the table will be updated as new combinations are released. consult your local sales representative to confirm availability of spec ific combinations and to check on newly released combinations. production part approval process (ppap) suppor t is only provided for aec-q100 grade products. products to be used in end-use applications that require iso/ts-16949 compliance must be aec-q100 grade products in combination with ppap. non?aec-q100 grade products are no t manufactured or documented in full compliance with iso/ts-16949 requirements. aec-q100 grade products are also offered without ppap suppor t for end-use applications that do not require iso/ts-16949 compliance. S29JL064J valid combination - automotive device number speed (ns) package type & material temperature range model number packing type package description S29JL064J 60 bh a000, 3 fbga tf tsop
document number: 002-00856 rev. *g page 10 of 60 S29JL064J 8. device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addre ssable memory location. the register is a latch used to store th e commands, along with the address and data information needed to ex ecute the command. the contents of the register serve as inputs to the internal state machine. the state ma chine outputs dictate the function of the device. table lists the device bus operations, the inputs and control levels they require, and the resulting output. t he following subsections describe each of th ese operations in further detail. legend l = logic low = v il h = logic high = v ih v id = 11.5?12.5v v hh = 9.0 0.5v x = don?t care sa = sector address a in = address in d in = data in d out = data out notes: 1. addresses are a21:a0 in word mode (byte# = v ih ), a21:a-1 in byte mode (byte# = v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see boot sector/sector block protection and unprotection on page 18 . 3. if wp#/acc = v il , sectors 0, 1, 140, and 141 remain protected. if wp#/acc = v ih , protection on sectors 0, 1, 140, and 141 depends on whether they were last protected or unprotected using the method described in boot sector/sector block protection and unprotection on page 18 . if wp#/acc = v hh , all sectors will be unprotected. 8.1 word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at l ogic ?1?, the device is in word configuration, dq 15?dq0 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte co nfiguration, and only data i/o pi ns dq7?dq0 are active and contro lled by ce# and oe#. the data i/o pins dq14?dq8 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function . S29JL064J device bus operations operation ce# oe# we# reset# wp#/ acc addresses (note 1) dq15?dq8 dq7? dq0 byte# = v ih byte# = v il read l l h h l/h a in d out dq14?dq8 = high-z, dq15 = a-1 d out write l h l h (note 3) a in d in d in standby v cc 0.3v xx v cc 0.3v l/h x high-z high-z high-z output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector protect (note 2) lhl v id l/h sa, a6 = l, a1 = h, a0 = l xxd in sector unprotect (note 2) lhl v id (note 3) sa, a6 = h, a1 = h, a0 = l xxd in temporary sector unprotect xxx v id (note 3) a in d in high-z d in
document number: 002-00856 rev. *g page 11 of 60 S29JL064J 8.2 requirements for reading array data to read array data from the outputs, the sys tem must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array da ta to the output pins. we# should remain at v ih . the byte# pin determines whether the device outputs array data in words or bytes. the internal state machine is set for reading array data upon devic e power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content o ccurs during the power transition. no command is necessary in this mode to obtain ar ray data. standard microprocessor read cycles that assert valid addre sses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for re ad access until the command register contents are altered. refer to read-only operations on page 43 for timing specifications and to figure 17.1 on page 43 for the timing diagram. i cc1 in dc characteristics on page 39 represents the active current specification for reading array data. 8.3 writing commands/command sequences to write a command or command sequence (whi ch includes programming data to the de vice and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin det ermines whether the device accepts program data in bytes or words. refer to word/byte configuration on page 10 for more information. the device features an unlock bypass mode to facilitate faster programming. once a bank enters the unlock bypass mode, only two write cycles are required to program a word or byte, instead of four. byte/word program command sequence on page 28 has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sectors, or the entire device. table on page 16 indicates the address space that each sector occupies. similarly, a sector address is the address bits required to uniquely select a sector. command definitions on page 27 has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. the device address space is divided into four banks. a bank address is the address bits required to uniquely select a bank. i cc2 in the dc characteristics on page 39 represents the active current specification for the write mode. ac characteristics on page 43 contains timing specification tables and timing diagrams for write operations. 8.3.1 accelerated program operation the device offers accelerated program operati ons through the acc function. this is one of two functions provided by the wp#/acc pin. this function is primarily intended to allo w faster manufacturing th roughput at the factory. if the system asserts v hh on this pin, the device autom atically enters the aforementioned unlock by pass mode, temporarily unprotects any protected sectors, and us es the higher voltage on the pin to reduce the time required for program operations. th e system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/ acc pin returns the device to normal operation. note that v hh must not be asserted on wp#/acc for operations other than accelerated programming, or device damage may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. see write protect (wp#) on page 19 for related information. 8.3.2 autoselect functions if the system writes the autoselect command sequence, the device enters the autose lect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to autoselect mode on page 17 and autoselect command sequence on page 28 for more information. 8.4 simultaneous read/write op erations with zero latency this device is capable of reading data from one bank of memory while programming or er asing in another bank of memory. an erase operation may also be suspended to read from or program to an other location within the same bank (except the sector being erased). figure 17.8 on page 48 shows how read and write cycles may be initiated for simultaneous operation with zero latency. i cc6 and i cc7 in the dc characteristics on page 39 represent the current specifications for read-while-program and read-while- erase, respectively.
document number: 002-00856 rev. *g page 12 of 60 S29JL064J 8.5 standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and t he outputs are placed in the high impedanc e state, independent of the oe# input. the device enters the cmos standby mode wh en the ce# and reset# pins are both held at v cc 0.3v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, be fore it is ready to read data. if the device is deselected during erasure or programming, t he device draws active current until the operation is completed. i cc3 in dc characteristics on page 39 represents the standby current specification. 8.6 automatic sleep mode the automatic sleep mode minimizes flash device energy cons umption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep m ode, output data is latched and always available to the system. i cc5 in dc characteristics on page 39 represents the automatic sl eep mode current specification. 8.7 reset#: hardware reset pin the reset# pin provides a hardware method of resett ing the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the reset# pulse. the device also resets the intern al state machine to reading array data. t he operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure dat a integrity. current is reduced for the du ration of the reset # pulse. when reset # is held at v ss 0.3v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3v, the standby current will be greater. the reset# pin may be tied to the system rese t circuitry. a system reset would thus also reset t he flash memory , enabling the system to read the boot-up firm ware from the flash memory. if reset# is asserted during a program or erase operation, the ry/by# pin remains a ?0? (busy) until the internal reset operati on is complete, which requires a time of t ready (during embedded algorithms) . the system can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin i s ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms ). the system can read data t rh after the reset# pin returns to v ih . refer to hardware reset (reset#) on page 44 for reset# parameters and to figure 17.2 on page 44 for the timing diagram.
document number: 002-00856 rev. *g page 13 of 60 S29JL064J 8.8 output disable mode when the oe# input is at v ih , output from the device is disabled. the out put pins are placed in the high impedance state. S29JL064J sector architecture (sheet 1 of 4) bank sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range bank 1 sa0 0000000000 8/4 000000h?001fffh 00000h?00fffh sa1 0000000001 8/4 002000h?003fffh 01000h?01fffh sa2 0000000010 8/4 004000h?005fffh 02000h?02fffh sa3 0000000011 8/4 006000h?007fffh 03000h?03fffh sa4 0000000100 8/4 008000h?009fffh 04000h?04fffh sa5 0000000101 8/4 00a000h?00bfffh 05000h?05fffh sa6 0000000110 8/4 00c000h?00dfffh 06000h?06fffh sa7 0000000111 8/4 00e000h?00ffffh 07000h?07fffh sa8 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa9 0000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa10 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa11 0000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa12 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa13 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa14 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa15 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa16 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa17 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa18 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa19 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa20 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa21 0001110xxx 64/32 0e0000h?0effffh 70000h?77fffh sa22 0001111xxx 64/32 0f 0000h?0fffffh 78000h?7ffffh
document number: 002-00856 rev. *g page 14 of 60 S29JL064J bank 2 sa23 0010000xxx 64/32 100000h?10ffffh 80000h?87fffh sa24 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa25 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa26 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa27 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa28 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa29 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa30 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa31 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa32 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa33 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa34 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa35 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa36 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa37 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa38 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa39 0100000xxx 64/32 200000h?20ffffh 100000h?107fffh sa40 0100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa41 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa42 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa43 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa44 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa45 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa46 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa47 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa48 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa49 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa50 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa51 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa52 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa53 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa54 0101111xxx 64/32 2f 0000h?2fffffh 178000h?17ffffh sa55 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa56 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa57 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa58 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa59 0110100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa60 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa61 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa62 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa63 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa64 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa65 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa66 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa67 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa68 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa69 0111110xxx 64/32 3e 0000h?3effffh 1f0000h?1f7fffh sa70 0111111xxx 64/32 3f 0000h?3fffffh 1f8000h?1fffffh S29JL064J sector architecture (sheet 2 of 4) bank sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
document number: 002-00856 rev. *g page 15 of 60 S29JL064J bank 3 sa71 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa72 1000001xxx 64/32 410000h?41ffffh 208000h?20ffffh sa73 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa74 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa75 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa76 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa77 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa78 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa79 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa80 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa81 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa82 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa83 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa84 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa85 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa86 1001111xxx 64/32 4f 0000h?4fffffh 278000h?27ffffh sa87 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa88 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa89 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa90 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa91 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa92 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa93 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa94 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa95 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa96 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa97 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa98 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa99 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa100 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa101 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa102 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa103 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa104 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa105 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa106 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa107 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa108 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa109 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa110 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa111 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa112 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa113 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa114 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa115 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa116 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa117 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa118 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh S29JL064J sector architecture (sheet 3 of 4) bank sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
document number: 002-00856 rev. *g page 16 of 60 S29JL064J note: the address range is a21:a-1 in byte mode (byte# = v il ) or a21:a0 in word mode (byte# = v ih ). bank 4 sa119 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa120 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa121 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa122 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa123 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa124 1110101xxx 64/32 750000h?75ffffh 3a8000h?3affffh sa125 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa126 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa127 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa128 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa129 1111010xxx 64/32 7a0000h?7affffh 3d0000h?3d7fffh sa130 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa131 1111 100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa132 1111 101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa133 1111110xxx 64/32 7e 0000h?7effffh 3f0000h?3f7fffh sa134 111111 1000 8/4 7f0000h?7f1fffh 3f8000h?3f8fffh sa135 111111 1001 8/4 7f2000h?7f3fffh 3f9000h?3f9fffh sa136 111111 1010 8/4 7f4000h?7f5fffh 3fa000h?3fafffh sa137 1111111011 8/4 7f 6000h?7f7fffh 3fb000h?3fbfffh sa138 1111111100 8/4 7f 8000h?7f9fffh 3fc000h?3fcfffh sa139 1111111101 8/4 7fa000 h?7fbfffh 3fd000h?3fdfffh sa140 1111111110 8/4 7fc000 h?7fdfffh 3fe000h?3fefffh sa141 1111111111 8/4 7fe 000h?7fffffh 3ff000h?3fffffh bank address bank a21?a19 1 000 2 001, 010, 011 3 100, 101, 110 4 111 secured silicon region addresses device sector size (x8) address range (x16) address range S29JL064J 256 bytes 000000h?0000ffh 000000h?00007fh S29JL064J sector architecture (sheet 4 of 4) bank sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
document number: 002-00856 rev. *g page 17 of 60 S29JL064J 8.9 autoselect mode the autoselect mode provides manufacturer and device identificati on, and sector protection verifi cation, through identifier cod es output on dq7?dq0. this mode is primarily intended for pr ogramming equipment to automatically match a device to be programmed with its corresponding programming algorithm. howeve r, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id on address pin a9. address pins must be as shown in table . in addition, when verifying sector protection, the sector addr ess must appear on the appropriate highest order address bits (see table on page 16 ). table shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the corresp onding identifier code on dq7?dq0. however, the autoselect codes can also be accessed in-system through the command regist er, for instances when the S29JL064J is erased or programmed in a system without access to high voltage on the a9 pin. the command sequence is illustrated in table on page 32 . note that if a bank address (ba) on address bits a21, a20, and a19 is asserted during the third write cycle of t he autoselect command, the hos t system can read autoselect data from that bank and then immediately read array data from another bank, without exiting the autoselect mode. to access the autoselect codes in-system, the host system can issue the autoselect co mmand via the command register, as shown in table on page 32 . this method does not require v id . refer to autoselect command sequence on page 28 for more information. legend l = logic low = v il h = logic high = v ih ba = bank address sa = sector address x = don?t care. S29JL064J autoselect codes, (high voltage method) description ce# oe# we# a21 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 a2 a1 a0 dq15 to dq8 dq7 to dq0 byte# = v ih byte# = v il manufacturer id : spansion products llhbaxv id xlxllll x x 01h device id read cycle 1 llhbaxv id x l x lllh 22h x 7eh read cycle 2 l h h h l 22h 02h read cycle 3 l h h h h 22h 01h sector protection verification llhsaxv id xlxllhl x x 01h (protected), 00h (unprotected) secured silicon indicator bit (dq6, dq7) llhbaxv id xlxllhh x x 81h (factory locked), 41h (customer locked), 01h (not locked)
document number: 002-00856 rev. *g page 18 of 60 S29JL064J 8.10 boot sector/sector block protection and unprotection note: for the following discussion, the term sector applies to both boot sectors and sector bl ocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see table ). the hardware sector protection f eature disables both program and er ase operations in any sector. the hardware sector unprotecti on feature re-enables both program an d erase operations in previously protected sectors. sector protection/unprotection can be implemented via two methods. S29JL064J boot sector/sector block addresses for protection/unprotection (sheet 1 of 2) sector a21?a12 sector/sector block size sa0 0000000000 8 kbytes sa1 0000000001 8 kbytes sa2 0000000010 8 kbytes sa3 0000000011 8 kbytes sa4 0000000100 8 kbytes sa5 0000000101 8 kbytes sa6 0000000110 8 kbytes sa7 0000000111 8 kbytes sa8?sa10 0000001xxx, 0000010xxx, 0000011xxx, 192 (3x64) kbytes sa11?sa14 00001xxxxx 256 (4x64) kbytes sa15?sa18 00010xxxxx 256 (4x64) kbytes sa19?sa22 00011xxxxx 256 (4x64) kbytes sa23?sa26 00100xxxxx 256 (4x64) kbytes sa27-sa30 00101xxxxx 256 (4x64) kbytes sa31-sa34 00110xxxxx 256 (4x64) kbytes sa35-sa38 00111xxxxx 256 (4x64) kbytes sa39-sa42 01000xxxxx 256 (4x64) kbytes sa43-sa46 01001xxxxx 256 (4x64) kbytes sa47-sa50 01010xxxxx 256 (4x64) kbytes sa51-sa54 01011xxxxx 256 (4x64) kbytes sa55?sa58 01100xxxxx 256 (4x64) kbytes sa59?sa62 01101xxxxx 256 (4x64) kbytes sa63?sa66 01110xxxxx 256 (4x64) kbytes sa67?sa70 0 1111xxxxx 256 (4x64) kbytes sa71?sa74 10000xxxxx 256 (4x64) kbytes sa75?sa78 10001xxxxx 256 (4x64) kbytes sa79?sa82 10010xxxxx 256 (4x64) kbytes sa83?sa86 10011xxxxx 256 (4x64) kbytes sa87?sa90 10100xxxxx 256 (4x64) kbytes sa91?sa94 10101xxxxx 256 (4x64) kbytes sa95?sa98 10110xxxxx 256 (4x64) kbytes sa99?sa102 10111xxxxx 256 (4x64) kbytes sa103?sa106 11000xxxxx 256 (4x64) kbytes sa107?sa110 11001xxxxx 256 (4x64) kbytes sa111?sa114 11010xxxxx 256 (4x64) kbytes sa115?sa118 11011xxxxx 256 (4x64) kbytes sa119?sa122 11100xxxxx 256 (4x64) kbytes sa123?sa126 11101xxxxx 256 (4x64) kbytes
document number: 002-00856 rev. *g page 19 of 60 S29JL064J sector protect/sector unprotect requires v id on the reset# pin only, and can be implemen ted either in-system or via programming equipment. figure 8.2 on page 21 shows the algorithms and figure 17.13 on page 51 shows the timing diagram. for sector unprotect, all unprotected sectors mu st first be protected prior to the first sector unprotect write cycle. note that the sector unprotect algorithm unprotects all sectors in parallel. all previous ly protected sectors must be individually re-protected. to change data in protected sectors efficiently, the temporary se ctor unprotect function is available. see temporary sector unprotect on page 20 . the device is shipped with all sectors u nprotected. optional spansion programming se rvice enable programming and protecting sectors at the factory prior to shipping the device. contact your local sales office for details. it is possible to determine whether a se ctor is protected or unprotected. see autoselect mode on page 17 for details. 8.11 write protect (wp#) the write protect function provides a hardwa re method of protecting without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in se ctors 0, 1, 140, and 141, independently of whether those sectors were protec ted or unprotected using the method described in boot sector/sector block protection and unprotection on page 18 . if the system asserts v ih on the wp#/acc pin, the device reverts to whether sector s 0, 1, 140, and 141 were last set to be protected or unprotected. that is, sector protecti on or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in boot sector/sector block protection and unprotection on page 18 . note that the wp#/acc pin must not be left floating or unconnected; inconsis tent behavior of the device may result. sa127?sa130 11110xxxxx 256 (4x64) kbytes sa131?sa133 1111 100xxx, 1111 101xxx, 1111110xxx 192 (3x64) kbytes sa134 1111111000 8 kbytes sa135 1111111001 8 kbytes sa136 1111111010 8 kbytes sa137 1111111011 8 kbytes sa138 1111111100 8 kbytes sa139 1111111101 8 kbytes sa140 1111111110 8 kbytes sa141 1111111111 8 kbytes wp#/acc modes wp# input voltage device mode v il disables programming and erasing in sa0, sa1, sa140, and sa141 v ih enables programming and erasing in sa0, sa1, sa140, and sa141, dependent on whether they were last protected or unprotected. v hh enables accelerated programming (acc). see accelerated program operation on page 11. S29JL064J boot sector/sector block addresses for protection/unprotection (sheet 2 of 2) sector a21?a12 sector/sector block size
document number: 002-00856 rev. *g page 20 of 60 S29JL064J 8.12 temporary sector unprotect note: for the following discussion, the term sector applies to both sectors and sector blocks. a sector block consists of two or more adjacent sectors that are protected or unprotected at the same time (see table on page 18 ). this feature allows temporary unprotection of previously protected sectors to cha nge data in-system. the temporary sector unprotect mode is activated by setting the reset# pin to v id . during this mode, formerly prot ected sectors can be programmed or erased by selecting the se ctor addresses. once v id is removed from the reset# pin, all the previously protected sectors are protected again. figure 8.1 shows the algorithm, and figure 17.12 on page 50 shows the timing diagrams, for this feature. if the wp#/acc pin is at v il , sectors 0, 1, 140, and 141 will remain protec ted during the temporary sector unprotect mode. figure 8.1 temporary sector unprotect operation notes: 1. all protected sectors unprotected (if wp#/acc = v il , sectors 0, 1, 140, and 141 will remain protected). 2. all previously protected sectors are protected once again. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
document number: 002-00856 rev. *g page 21 of 60 S29JL064J figure 8.2 in-system sector protec t/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1
document number: 002-00856 rev. *g page 22 of 60 S29JL064J 8.13 secured silicon region the secured silicon region feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secured silicon region is 256 bytes in length, and may shipped unprotected, allowing customers to utilize that sector in any ma nner they choose, or may shipped locked at the factory (upon customer request). the secured silicon indicator bit data will be 81h if factory lock ed, 41h if customer locked, or 01h if neither. refer to table on page 17 for more details. the system accesses the secured silicon region through a command sequence (see enter secured silicon region/exit secured silicon region command sequence on page 28 ). after the system has written the enter secured silicon region command sequence, it may read the secured silicon region by using the addr esses normally occupied by the boot sectors. this mode of operation continues until the system issues t he exit secured silicon region command sequ ence, or until power is removed from th e device. on power-up, or following a hardware reset, the device re verts to sending commands to t he first 256 bytes of sector 0. note that the acc function and unlock bypass modes are not available when the secured silicon region is enabled. 8.13.1 factory locked: secured silicon re gion programmed and protected at the factory in a factory locked device, the secured silicon region is protec ted when the device is shipped from the factory. the secured si licon region cannot be modified in any way. th e device is preprogrammed with both a random number and a secure esn. the 8-word random number is at addresses 000000h?000007h in word mode (or 000000h?00000fh in byte mode). the secure esn is programmed in the next 8 words at addresses 000008h?00000fh (o r 000010h?00001fh in byte mode). the device is available preprogrammed with one of the following: ? a random, secure esn only ? customer code through spansion programming services ? both a random, secure esn and customer code through spansion programming services contact an your local sales office for details on using spansion programming services. 8.13.2 customer lockable: secured silicon region not programmed or protected at the factory if the security feature is not required, the secured silicon region can be treated as an additional flash memory space. the sec ured silicon region can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock bypass functions are not available when programming the secured silicon region. ? write the three-cycle enter secured silicon region command sequence, and then follow the in-syste m sector protect algorithm as shown in figure 8.2 on page 21 , except that reset# may be at either v ih or v id . this allows in-system protection of the secured silicon region without raising any device pin to a high voltage. note that this method is only applicable to the secured silico n region. ? to verify the protect/unprotect st atus of the secured silicon region, follow the algorithm shown in figure 8.3 on page 23 . once the secured silicon region is locked and verified, the system must write the exit secured sili con region command sequence to return to reading and writing the remainder of the array. the secured silicon region lock must be used with caution since, once locked, there is no procedure available for unlocking the secured silicon region and none of the bits in the secured silicon region memory space can be modified in any way.
document number: 002-00856 rev. *g page 23 of 60 S29JL064J figure 8.3 secured silicon region protect verify 8.14 hardware data protection the command sequence requirement of unlock cycles for programming or eras ing provides data protecti on against inadvertent writes (refer to table on page 32 for command definitions). in addition, the follo wing hardware data protection measures prevent accidental erasure or programming, wh ich might otherwise be caused by spur ious system level signals during v cc power-up and power-down transitions, or from system noise. 8.14.1 low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper si gnals to the control pins to prevent unintentional writes when v cc is greater than v lko . 8.14.2 write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. 8.14.3 logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. 8.14.4 power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept co mmands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. write 60h to any address write 40h to secure silicon region address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 ms read from secure silicon region address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secure silicon region is unprotected. if data = 01h, secure silicon region is protected. remove v ih or v id from reset# secure silicon region protect verify complete secured silicon region exit command
document number: 002-00856 rev. *g page 24 of 60 S29JL064J 9. common flash memory interface (cfi) the common flash interface (cfi) specificat ion outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entir e families of devices. software support can then be device- independent, jedec id-independent, and forward- and backward-compati ble for the specified flash device families. flash vendors can standardize their existing interf aces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query comma nd, 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresse s given in table on page 24 to table on page 26 . to terminate reading cfi data, the syst em must write the reset command.the cfi query mode is not accessible when the device is exec uting an embedded program or embedded erase algorithm. the system can also write the cfi query comm and when the device is in the autoselect mode via the command register only (high voltage method does not apply). the device enters the cfi query mode, and th e system can read cfi data at the addresses given i n table on page 24 to table on page 26 . the system must write the reset command to return to reading array data. for further information, please refer to the cfi specification an d cfi publication 100. contact your local sales office for cop ies of these documents. cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0003h typical timeout per single byte/word write 2 n s 20h 40h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 0009h typical timeout per individual block erase 2 n ms 22h 44h 000fh typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0004h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
document number: 002-00856 rev. *g page 25 of 60 S29JL064J device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0017h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to the cfi publication 100) 2ah 2bh 54h 56h 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0003h number of erase block regions within device 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specific ation or cfi publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 007dh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specific ation or cfi publication 100) 35h 36h 37h 38h 6ah 6ch 6eh 70h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specific ation or cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specific ation or cfi publication 100)
document number: 002-00856 rev. *g page 26 of 60 S29JL064J primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii (reflects modifications to the silicon) 44h 88h 0033h minor version number, ascii (refl ects modifications to the cfi table) 45h 8ah 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0011 = 0.11 m floating gate 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 94h 0077h simultaneous operation 00 = not supported, x = number of sectors (excluding bank 1) 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 0001h top/bottom boot sector flag 00h = uniform device, 01h = 8 x 8 kbyte sectors, top and bottom boot with write protect, 02h = bottom boot device, 03h = top boot device, 04h= both top and bottom 50h a0h 0000h program suspend 0 = not supported, 1 = supported 57h aeh 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h b0h 0017h bank 1 region information x = number of sectors in bank 1 59h b2h 0030h bank 2 region information x = number of sectors in bank 2
document number: 002-00856 rev. *g page 27 of 60 S29JL064J 10. command definitions writing specific address and data sequences into the command register initiates device operations. table on page 32 defines the valid register command sequences. writing incorrect address and data values or writ ing them in the improper sequence may place the device in an unknown state. a reset command is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whic hever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to ac characteristics on page 43 for timing diagrams. 10.1 reading array data the device is automatically set to reading array data after devic e power-up. no commands are requi red to retrieve data. each ba nk is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-suspend-read mode, after which the system can read data from any non-eras e-suspended sector within the same bank. the system can read array data using the standard read timing, except that if it re ads at an address within erase-suspended sect ors, the device outputs status data. aft er completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands on page 31 for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. see reset command on page 27 for more information. see requirements for reading array data on page 11 for more information. read-only operations on page 43 provides the read parameters, and figure 17.1 on page 43 shows the timing diagram. 10.2 reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bi ts are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the bank to which the system was wr iting to the read mode. once erasure b egins, however, the device ignores reset commands until the operation is complete. the reset command may be writte n between the sequence cycles in a program command sequence before progra mming begins. this resets the bank to which the system was writing to the read mode. if the program command seq uence is written to a bank tha t is in the erase suspend mode, writing the reset command returns that bank to the erase-suspen d-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be writte n between the sequence cycles in an autoselect co mmand sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode, writing the reset command return s that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase o peration, writing the reset command retu rns the bank to the read mode (or erase- suspend-read mode if that bank was in erase suspend). please not e that the ry/by# signal remains low until this reset is issued . 5ah b4h 0030h bank 3 region information x = number of sectors in bank 3 5bh b6h 0017h bank 4 region information x = number of sectors in bank 4 primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description
document number: 002-00856 rev. *g page 28 of 60 S29JL064J 10.3 autoselect command sequence the autoselect command sequence allows the host system to acce ss the manufacturer and device codes, and determine whether or not a sector is protected. the autoselect co mmand sequence may be written to an address wi thin a bank that is either in the rea d or erase-suspend-read mode. the autoselect command may not be wr itten while the device is actively programming or erasing in another bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that c ontains the bank address and the autoselect command. the bank then en ters the autoselect mode. the system may read any number of autoselect codes without re-initiating the command sequence. table on page 32 shows the address and data requirements. to determine sector protection information , the system must write to the appropriate bank address (ba) and sector address (sa). table on page 16 shows the address range and bank number associated with each sector. the system must write the reset co mmand to return to the read mode (or erase-sus pend-read mode if the ba nk was previously in erase suspend). 10.4 enter secured silicon region/ex it secured silic on region command sequence the system can access the secured silicon region by issuing the three-cycle enter secured silicon region command sequence. the device continues to access the secur ed silicon region until the system issues th e four-cycle exit secured silicon region command sequence. the exit secured silicon region command se quence returns the device to normal operation. the secured silicon region is not accessible when the device is ex ecuting an embedded program or embedded erase algorithm. table on page 32 shows the address and data requirements for both command sequences. see also secured silicon region on page 22 for further information. note that the acc function and unlock bypass modes are not available when the secured silicon region is enabled. 10.5 byte/word program command sequence the system may program the device by word or byte, depending on t he state of the byte# pin. prog ramming is a four-bus-cycle operation. the program command sequence is initiated by wr iting two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically provides internal ly generated program pulses and verifies the programmed cell margin. table on page 32 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, that bank th en returns to the read mode and addresses are no longer latched. the system can determine th e status of the program operation by us ing dq7, dq6, or ry/by#. refer to write operation status on page 33 for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. note that the secured silicon region, autoselect, and cfi functions are unavailable when a program operation is in progress. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from 0 back to a 1 . attempting to do so may cause that bank to set dq5 = 1, or ca use the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the dat a is still 0. only erase operations can convert a 0 to a 1 .
document number: 002-00856 rev. *g page 29 of 60 S29JL064J 10.5.1 unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to a bank faster than using the standard program command sequence. the unlock by pass command sequence is in itiated by first writing two unlock cycles . this is followed by a third write cycle containing the unlock bypass command, 20h. that bank then en ters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles re quired in the standard program command sequence , resulting in faster total pr ogramming time. table on page 32 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cy cle unlock bypass reset command sequence. (see table on page 32 ). the device offers accelerated prog ram operations through the wp#/a cc pin. when the system asserts v hh on the wp#/acc pin, the device automatically enters the unlock bypass mode. the system may then write the two-cy cle unlock bypass program command sequence. the device uses the higher voltage on the wp#/ acc pin to accelerate the oper ation. note t hat the wp#/acc pin must not be at v hh for any operation other than accelerated programming, or device damage may result. in addition, the wp#/ acc pin must not be left floating or unconnected; in consistent behavior of the device may result. figure 10.1 on page 29 illustrates the algorithm for the program operation. refer to erase and program operations on page 46 for parameters, and figure 17.5 on page 47 for timing diagrams. figure 10.1 program operation note: 1. see table on page 32 for program command sequence. start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress
document number: 002-00856 rev. *g page 30 of 60 S29JL064J 10.6 chip erase command sequence chip erase is a six bus cycle operation. the chip erase comm and sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional un lock write cycles are th en followed by the chip erase comm and, which in tu rn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memo ry for an all zero data pattern prio r to electrical erase. the system is not required to provide any controls or timings during these operations. table on page 32 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the status of th e erase operation by us ing dq7, dq6, dq2, or ry/by#. refer to write operation status on page 33 for information on these status bits. any commands written during the chip erase o peration are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occu rs, the chip erase command sequence should be re initiated once that bank has returned to readi ng array data, to ensure data integrity. note that the secured silicon region, autosele ct, and cfi functions are unavailable when an erase operation is in progress. figure 10.2 on page 31 illustrates the algorithm for the erase operation. refer to erase and program operations on page 46 for parameters, and figure 17.7 on page 48 for timing diagrams. 10.7 sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is init iated by writing two unlock cycles, followe d by a set-up command. two additional unlock cycles are written, and are then followed by the address of the sector to be erased, an d the sector erase command. table on page 32 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically programs and verifies the entire se ctor for an all zero data pattern prior to electrical erase. the system is not required to provide any co ntrols or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase commands may be written. howeve r, these additional erase commands are only one bus cycle long and should be identical to the sixth cycle of the standard erase command explained above. loading the sector erase buffer may b e done in any sequence, and the number of sectors may be from one se ctor to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sect or erase address and command following the exceeded time-out may or may not be accepted. it is recommen ded that processor interrupts be disabled dur ing this time to ensure all commands are accepted. the interrupts can be re-enabled afte r the last sector eras e command is written. if any command other than 30h, b0h, f0h is input during the time-out period, the normal operation will not be guaranteed. the system must re write the command sequence and any additional addresses and commands. the system can monitor dq3 to determine if th e sector erase timer has timed out (see th e section on dq3: sect or erase timer.). the time-out begins from the rising edge of the final we# or ce# pulse (first rising ed ge) in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data fr om the non-erasing bank. the system can determine the status of the erase opera tion by reading dq7, dq6, dq2, or ry /by# in the erasing bank. refer to write operation status on page 33 for information on these status bits. once the sector erase operatio n has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset immediately terminates the erase op eration. if that occurs, the se ctor erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. note that the secured silicon region, autoselect, and cfi functions are unavailable when an erase operation is in progress. figure 10.2 on page 31 illustrates the algorithm for the erase operation. refer to erase and program operations on page 46 for parameters, and figure 17.7 on page 48 for timing diagrams.
document number: 002-00856 rev. *g page 31 of 60 S29JL064J figure 10.2 erase operation notes: 1. see table on page 32 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer. 10.8 erase suspend/erase resume commands the erase suspend command, b0h, allows t he system to interrupt a sector erase operat ion and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid onl y during the sector erase operation, including the 50 s time-o ut period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program al gorithm. the bank address must contain one of the sectors cu rrently selected for erase. when the erase suspend command is written during the sector erase operation, the device requires a maximum of 35 s to suspend the erase operation. however, when the erase suspend command is written during the sector erase ti me-out, the device immediately terminates the time-out peri od and suspends the erase operation. after the erase operation has been suspend ed, the bank enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) it is not recommended to program the secured silicon region after an er ase suspend, as proper device fu nctionality cannot be guaranteed. reading at any address within erase-suspended sectors produces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to write operation status on page 33 for information on these status bits. after an erase-suspended program operation is complete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq 6 status bits, just as in the standard byte program operation. refer to write operation status on page 33 for more information. in the erase-suspend-read mode, the system can also issue th e autoselect command sequence. the device allows reading autoselect codes even at addresses within er asing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase susp end mode, and is ready for anot her valid operation. refer to autoselect mode on page 17 and autoselect command sequence on page 28 for details. to resume the sector erase o peration, the system must write the erase resu me command. t he bank address of the erase- suspended bank is required when writing th is command. further writes of the resu me command are ignored. another erase suspend command can be written after the chip has resumed erasing. start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress
document number: 002-00856 rev. *g page 32 of 60 S29JL064J legend x = don?t care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addres ses latch on the falling edge of the we# or ce# pulse, whichever ha ppens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a21?a12 uniquely select any sector. refe r to table on page 16 for information on sector addresses. ba = address of the bank that is being swit ched to autoselect mode, is in bypass mo de, or is being erased. a21?a19 uniquely sel ect a bank. notes: 1. see table on page 10 for description of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the four th, fifth, and sixth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15?dq8 are don?t care in command sequences, except for rd and pd. 5. unless otherwise noted, address bits a21?a11 are don?t cares for unlock and command cycles, unless sa or pa is required. 6. no unlock or command cycles required when bank is reading array data. 7. the reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in erase suspend) w hen a bank is in the autoselect mode, or if dq5 goes high (while the bank is providing status information). S29JL064J command definitions command sequence (note 1) cycles bus cycles (notes 2 ? 5 ) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1ra rd reset (note 7) 1xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 (ba)555 90 (ba)x00 01 byte aaa 555 (ba)aaa device id (note 9) word 6 555 aa 2aa 55 (ba)555 90 (ba)x01 7e (ba)x0e 02 (ba)x0f 01 byte aaa 555 (ba)aaa (ba)x02 (ba)x1c (ba)x1e secured silicon region factory protect (note 10) word 4 555 aa 2aa 55 (ba)555 90 (ba)x03 81/41/ 01 byte aaa 555 (ba)aaa (ba)x06 boot sector/sector block protect verify (note 11) word 4 555 aa 2aa 55 (ba)555 90 (sa)x02 00/01 byte aaa 555 (ba)aaa (sa)x04 enter secured silicon region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit secured silicon region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 12) 2 xxx a0 pa pd unlock bypass reset (note 13) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase (note 17) word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 14) 1ba b0 erase resume (note 15) 1ba 30 cfi query (note 16) word 1 55 98 byte aa
document number: 002-00856 rev. *g page 33 of 60 S29JL064J 8. the fourth cycle of the autoselect comma nd sequence is a read cycle. the system must provide the bank address to obtain the m anufacturer id, device id, or secured silicon region factory protect information. data bits dq15?dq8 are don?t care. while reading the autoselect addresses, the bank address must be the same until a reset command is given. see autoselect command sequence on page 28 for more information. 9. the device id must be read across t he fourth, fifth, and sixth cycles. 10. the data is 81h for factory locked, 41h for customer locked, and 01h for not factory/customer locked. 11. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. 12. the unlock bypass command is required prior to the unlock bypass program command. 13. the unlock bypass reset command is required to return to the read mode when the bank is in the unlock bypass mode. 14. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the er ase suspend command is valid only during a sector erase operation, and requires the bank address. 15. the erase resume command is valid only during th e erase suspend mode, and requires the bank address. 16. command is valid when device is ready to read array data or w hen device is in autoselect mode. 17. additional sector erase commands during the time-out period after an initial sector erase are one cycle long and identical t o the sixth cycle of the sector erase command sequence (sa / 30). 11. write operation status the device provides several bits to dete rmine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table on page 38 and the following subsections describe the function of thes e bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is co mplete or in progress. the device also provides a hardware-ba sed output signal, ry/ by#, to determine whether an embedded program or er ase operation is in progress or has been completed. 11.1 dq7: data# polling the data# polling bit, dq7, indicates to the host system whet her an embedded program or erase algorithm is in progress or completed, or whether a bank is in eras e suspend. data# polling is valid after the rising edge of the final we# pulse in the co mmand sequence. during the embedded program algorithm, the device outputs on dq 7 the complement of the datum programmed to dq7. this dq7 status also applies to programming durin g erase suspend. when the embedded program al gorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for approximatel y 1 s, then that bank returns to the re ad mode. during the embedded erase algorit hm, data# polling produces a 0 on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a 1 on dq7. the system must pr ovide an address wi thin any of the sectors selected for erasure to re ad valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are prot ected, data# polling on dq7 is active f or approximately 3 ms, then the bank returns to the read mode. if not all selected sectors are protected, the embedded erase algori thm erases the unprotected sectors, and ignores the selected sector s that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq15?dq0 (or dq7?dq0 for x8-only device) on the following read cycles. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq15?dq8 (dq7?dq0 for x8-only devi ce) while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be st ill invalid. valid data on dq15?dq0 (or dq7?dq0 for x8-only device) will appear on successive read cycles. table on page 38 shows the outputs for data# polling on dq7. figure 11.1 on page 34 shows the data# polling algorithm. figure 17.9 on page 49 shows the data# polling timing diagram.
document number: 002-00856 rev. *g page 34 of 60 S29JL064J figure 11.1 data# polling algorithm notes: 1. va = valid address for programming. during a sector erase operat ion, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-prot ected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 11.2 ry/by#: ready/busy# the ry/by# is a dedicated, open- drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid af ter the rising edge of the final we# pulse in the co mmand sequence. since ry/by# is an open-drain outp ut, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mod e.) if the output is high (ready), the device is in the read mode, t he standby mode, or one of the banks is in the erase-suspend-re ad mode. table on page 38 shows the outputs for ry/by#. when dq5 is set to ?1?, ry/by# will be in the busy state, or ?0?. $1??$ata 9e s .o .o $1?? .o 9e s 9e s &!), 0!33 2ead?$1n$1 !ddr??6! 2ead?$1n$1 !ddr??6! $1??$ata 34!24
document number: 002-00856 rev. *g page 35 of 60 S29JL064J 11.3 dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we # pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algor ithm operation, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are pr otected, dq6 toggles for approximately 3 m s, then returns to reading array data. if not all selected sectors are pr otected, the embedded erase al gorithm erases the unprotec ted sectors, and ignores the select ed sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the em bedded erase algorithm is in progress), dq 6 toggles. when the device enters the eras e suspend mode, dq6 stops toggling. however, the system must al so use dq2 to determine which sectors are erasing or erase- suspended. alte rnatively, the system can use dq7 (see dq7: data# polling on page 33 ). if a program address falls within a protected sector, dq6 toggle s for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspen d-program mode, and stops toggling once th e embedded program algorithm is complete.
document number: 002-00856 rev. *g page 36 of 60 S29JL064J figure 11.2 toggle bit algorithm note: the system should recheck the toggle bit even if dq5 = 1 because the toggle bit may stop toggling as dq5 changes to 1 . see the subsections on dq6 and dq2 for more information. 11.4 dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indica tes whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is eras e-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addre sses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot di stinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indicates whet her the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bi ts are required for sector and mode information. refer to table on page 38 to compare outputs for dq2 and dq6. figure 11.2 on page 36 shows the toggle bit algorithm in flowchart form, and dq2: toggle bit ii on page 36 explains the algorithm. see also dq6: toggle bit i on page 35 . figure 17.10 on page 49 shows the toggle bit timing diagram. figure 17.11 on page 50 shows the differences between dq2 and dq6 in graphical form. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7Cdq0) address = va read byte (dq7Cdq0) address =va read byte (dq7Cdq0) address =va
document number: 002-00856 rev. *g page 37 of 60 S29JL064J 11.5 reading toggle bits dq6/dq2 refer to figure 11.2 on page 36 for the following discussion. whenever the system initially begins reading toggle bit status, it must read dq15?dq0 (or dq7?dq0 for x8-only device) at least twice in a row to determine whether a togg le bit is toggling. typically, the system would note and store the va lue of the toggle bit after t he first read. after the second read, the system would compare t he new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operat ion. the system can read array data on dq15?dq0 (or dq7?dq0 for x8-only device) on the following read cycle. however, if after the initial two read cycles, the system det ermines that the toggle bit is still toggling, the system also sho uld note whether the value of dq5 is high (see the section on dq5). if it is, the system sh ould then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bi t is no longer toggling, the de vice has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation succ essfully, and the system must write the reset co mmand to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the s ystem may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as described in the previ ous paragraph. alternat ively, it may choose to per form other system tasks. in th is case, the system must st art at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 11.2 on page 36 ). 11.6 dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1 , indicating that the program or erase cycle was not successfully completed. the device may output a 1 on dq5 if the system tries to program a 1 to a location that was previously programmed to 0 . only an erase operation can change a 0 back to a 1 . under this condition, the device halts t he operation, and when the timing limit has been exceeded, dq5 produces a 1 . under both these conditions, the s ystem must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode). 11.7 dq3: sector erase timer after writing a sector erase command seque nce, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-o ut also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a 0 to a 1 . if the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also sector erase command sequence on page 30 . after the sector erase command is written, the system should read the status of dq7 (data# pollin g) or dq6 (toggle bit i) to en sure that the device has accepted the command s equence, and then read dq3. if dq3 is 1 , the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is 0 , the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent se ctor erase command. if dq3 is high on the second status check, the last command might not have been ac cepted. the rdy/bsy# pin will be in the busy state under this condition. table on page 38 shows the status of dq3 relati ve to the other status bits.
document number: 002-00856 rev. *g page 38 of 60 S29JL064J notes: 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for m ore information. 2. dq7 and dq2 require a valid address when reading status info rmation. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addr esses a non-busy bank. 12. absolute maximum ratings notes: 1. minimum dc voltage on input or i/o pins is ?0.5v. duri ng voltage transitions, input or i/o pins may overshoot v ss to ?2.0v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5v. see figure 12.1 on page 38 . during voltage transitions, input or i/o pins may overshoot to v cc +2.0v for periods up to 20 ns. see figure 12.2 on page 39 . 2. minimum dc input voltage on pins a9, oe#, reset#, and wp#/acc is ?0.5v. during voltage transitions, a9, oe#, wp#/acc, and res et# may overshoot v ss to ? 2.0v for periods of up to 20 ns. see figure 12.1 on page 38 . maximum dc input voltage on pin a9 is +12.5v whic h may overshoot to +14.0v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5v which may overshoot to +12.0v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one seco nd. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress ratin g only; functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this data sheet is not implied. ex posure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 12.1 maximum negative overshoot waveform write operation status status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm in busy erasing sector 0 toggle 0 1 toggle 0 in not busy erasing sector 0 toggle 0 1 no toggle 0 erase suspend mode erase-suspend-read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0 storage temperature, plastic packages ?65c to +150c ambient temperature with power applied ?65c to +125c voltage with respect to ground v cc (note 1) ?0.5v to +4.0v a9 and reset# (note 2) ?0.5v to +12.5v wp#/acc ?0.5v to +9.5v all other pins (note 1) ?0.5v to v cc +0.5v output short circuit current (note 3) 200 ma 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v
document number: 002-00856 rev. *g page 39 of 60 S29JL064J figure 12.2 maximum positive overshoot waveform 13. operating ranges industrial (i) devices ambient temperature (t a ) ?40c to +85c automotive (a) devices ambient temperature (t a ) ?40c to +85c v cc supply voltages v cc for standard voltage range 2.7v to 3.6v operating ranges define those limits between which the functionality of the device is guaranteed. 14. dc characteristics 14.1 cmos compatible parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 and reset# input load current v cc = v cc max , oe# = v ih ; a9 or reset# = 12.5v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max , oe# = v ih 1.0 a i lr reset leakage current v cc = v cc max ; reset# = 12.5v 35 a i cc1 v cc active read current (notes 1 , 2 ) ce# = v il , oe# = v ih , byte mode 5 mhz 10 16 ma 1mhz 2 4 ce# = v il , oe# = v ih , word mode 5 mhz 10 16 1mhz 2 4 i cc2 v cc active write current (notes 2 , 3 )ce# = v il , oe# = v ih , we# = v il 15 30 ma i cc3 v cc standby current (note 2) ce#, reset# = v cc 0.3v 0.2 5 a i cc4 v cc reset current (note 2) reset# = v ss 0.3v 0.2 5 a i cc5 automatic sleep mode (notes 2 , 4 ) v ih = v cc 0.3v; v il = v ss 0.3v 0.2 5 a i cc6 v cc active read-while-program current (2) ce# = v il , oe# = v ih , 1 mhz byte 21 45 ma word 21 45 i cc7 v cc active read-while-erase current (2) ce# = v il , oe# = v ih , 1 mhz byte 21 45 ma word 21 45 i cc8 v cc active program-while-erase-suspended current (notes 2 , 5 ) ce# = v il , oe# = v ih 17 35 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
document number: 002-00856 rev. *g page 40 of 60 S29JL064J notes: 1. the i cc current listed is typically le ss than 2 ma/mhz, with oe# at v ih . 2. maximum i cc specifications are tested with v cc = v cc max. 3. i cc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 5. not 100% tested. 14.2 zero-power flash figure 14.1 i cc1 current vs. time (showing active and automatic sleep currents) note: addresses are switching at 1 mhz v hh voltage for wp#/acc sector protect/unprotect and program acceleration v cc = 3.0v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0v 10% 8.5 12.5 v v ol output low voltage i ol = 2.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v lko low v cc lock-out voltage (note 5) 1.8 2.0 2.5 v parameter symbol parameter description test conditions min typ max unit 25 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns
document number: 002-00856 rev. *g page 41 of 60 S29JL064J figure 14.2 typical i cc1 vs. frequency note: t = 25c 15. test conditions figure 15.1 test setup test specifications test condition 55, 60 70 unit output load capacitance, c l 30 100 pf input rise and fall times (note 1) 5ns input pulse levels 0.0 or v cc v input timing measurement reference levels 0.5 v cc v output timing measurement reference levels 0.5 v cc v 10 8 2 0 12345 frequency in mhz supply current in ma 2.7v 3.6v 4 6 12 c l device under te s t
document number: 002-00856 rev. *g page 42 of 60 S29JL064J note: 1. input rise and fall times are 0-100%. 16. key to switching waveforms figure 16.1 input waveforms and measurement levels waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high-z) 3.0v 0.0v 1.5v 1.5v output measurement level input
document number: 002-00856 rev. *g page 43 of 60 S29JL064J 17. ac characteristics 17.1 read-only operations notes: 1. not 100% tested. 2. see figure 15.1 on page 41 and table on page 41 for test specifications 3. measurements performed by placing a 50 oh m termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . figure 17.1 read operation timings parameter description test setup speed options jedec std. 55 60 70 unit t avav t rc read cycle time (note 1) min556070ns t avqv t acc address to output delay ce#, oe# = v il max556070ns t elqv t ce chip enable to output delay oe# = v il max556070ns t glqv t oe output enable to output delay max 25 30 ns t ehqz t df chip enable to output high-z (notes 1 , 3 ) max 16 ns t ghqz t df output enable to output high-z (notes 1 , 3 ) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 5 10 ns t oh t ce outputs we# addresses ce# oe# high-z output valid high-z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df
document number: 002-00856 rev. *g page 44 of 60 S29JL064J 17.2 hardware reset (reset#) note: not 100% tested. figure 17.2 reset timings parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 35 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 35 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
document number: 002-00856 rev. *g page 45 of 60 S29JL064J 17.3 word/byte configuration (byte#) figure 17.3 byte# timings for read operations figure 17.4 byte# timings for write operations note: refer to the erase/program operations table for t as and t ah specifications. parameter description speed options unit jedec std. 556070 t elfl/ t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high-z max 16 ns t fhqv byte# switching high to output active min 55 60 70 ns dq15 output data output (dq7?dq0) ce# oe# byte# t elfl dq14?dq0 data output (dq14?dq0) dq15/a-1 address input t flqz byte# switching from word to byte dq15 output data byte# t elfh dq14?dq0 data output (dq14?dq0) dq15/a-1 address input t fhqv byte# switching from byte to word mode ce# we# byte# the falling edge of the last we# signal t hold (t ah ) t set (t as )
document number: 002-00856 rev. *g page 46 of 60 S29JL064J 17.4 erase and program operations notes: 1. not 100% tested. 2. see erase and programming performance on page 53 for more information. parameter description speed options unit jedec std 55 60 70 t avav t wc write cycle time (note 1) min556070ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 30 35 40 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 35 40 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 25 25 30 ns t whdl t wph write pulse width high min 25 25 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 s word typ 6 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns t esl erase suspend latency max 35 s
document number: 002-00856 rev. *g page 47 of 60 S29JL064J figure 17.5 program operation timings notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 2. illustration shows device in word mode. figure 17.6 accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa wp#/acc t vhh v hh v il or v ih v il or v ih t vhh
document number: 002-00856 rev. *g page 48 of 60 S29JL064J figure 17.7 chip/sector erase operation timings notes: 1. sa = sector address (for sector erase), va = valid address for reading status data (see write operation status on page 33 ). 2. these waveforms are for the word mode. figure 17.8 back-to-back read/write cycle timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy oe# ce# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce# or ce2# controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w
document number: 002-00856 rev. *g page 49 of 60 S29JL064J figure 17.9 data# polling timings (during embedded algorithms) note: va = valid address. illustration shows first status cycle after co mmand sequence, last status read cycle, and array data read c ycle figure 17.10 toggle bit timings (during embedded algorithms) note: va = valid address; not required for dq6. illustration shows firs t two status cycle after command sequence, last status read cy cle, and array data read cycle. we# ce# oe# high z t oe high z dq7 dq0?dq6 ry/by# t busy complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t cph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by#
document number: 002-00856 rev. *g page 50 of 60 S29JL064J figure 17.11 dq2 vs. dq6 note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. 17.5 temporary sector unprotect note: not 100% tested. figure 17.12 temporary sector unprotect timing diagram parameter description all speed options jedec std unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
document number: 002-00856 rev. *g page 51 of 60 S29JL064J figure 17.13 sector/sector block protect and unprotect timing diagram note: * for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 17.6 alternate ce# controlled erase and program operations notes: 1. not 100% tested. 2. see erase and programming performance on page 53 for more information. parameter speed options jedec std. description 55 60 70 unit t avav t wc write cycle time (note 1) min556070ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 30 35 40 ns t dveh t ds data setup time min 30 35 40 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 25 40 ns t ehel t cph ce# pulse width high min 25 25 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 s word typ 6 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec sector group protect: 150 ? sector group unprot ect: 15 ms 1 ? reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect/unprotect verify v id v ih
document number: 002-00856 rev. *g page 52 of 60 S29JL064J figure 17.14 alternate ce# controlled write (erase/program) operation timings notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. waveforms are for the word mode. t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase t busy
document number: 002-00856 rev. *g page 53 of 60 S29JL064J 18. erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25c, 3.0v v cc , 100,000 cycles; checkerboard data pattern. 2. under worst case conditions of 90c, v cc = 2.7v, 1,000,000 cycles. 3. in the pre-programming step of the embedded erase al gorithm, all bytes are programmed to 00h before erasure. 4. system-level overhead is the time requi red to execute the two- or four-bus-cyc le sequence for the program command. see table on page 32 for further information on command definitions. 5. the device has a minimum program and erase cyc le endurance of 100,000 cycles per sector. 19. pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 5 sec excludes 00h programming prior to erasure (note 3) chip erase time 71 sec byte program time 6 80 s excludes system level overhead (note 4) word program time 6 80 s accelerated byte/word program time 4 70 s parameter symbol parameter description test setup max unit c in input capacit ance (applies to a21-a0, dq15-dq0) v in = 0 8.5 pf c out output capacitance (applies to dq15-dq0, ry/by#) v out = 0 5.5 pf c in2 control pin capacitance (applies to ce#, we#, oe#, wp#/acc, reset#, byte#) v in = 0 12 pf
document number: 002-00856 rev. *g page 54 of 60 S29JL064J 20. physical dimensions 20.1 ts 048?48-pin standard tsop 3664 \ f16-038.10 \ 11.6.7 package ts/tsr 48 jedec mo-142 (d) dd symbol min nom max a --- --- 1.20 a1 0.05 --- 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 --- 0.16 c 0.10 --- 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 0? --- 8 r 0.08 --- 0.20 n48 notes: 1. controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conform to ansi y14.5m-1982) 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark. 4. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. 6. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08mm (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07mm (0.0028"). 7. these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. 8. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. 9. dimension "e" is measured at the centerline of the leads.
document number: 002-00856 rev. *g page 55 of 60 S29JL064J 20.2 vbk048?48-pin fbga g1001.2 \ f16-038.25 \ 07.13.10 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package vbk 048 jedec n/a 8.15 mm x 6.15 mm nom package symbol min nom max note a --- --- 1.00 overall thickness a1 0.18 --- --- ball height d 8.15 bsc. body size e 6.15 bsc. body size d1 5.60 bsc. ball footprint e1 4.00 bsc. ball footprint md 8 row matrix size d direction me 6 row matrix size e direction n 48 total ball count b 0.33 --- 0.43 ball diameter e 0.80 bsc. ball pitch sd / se 0.40 bsc. solder ball placement --- depopulated solder balls
document number: 002-00856 rev. *g page 56 of 60 S29JL064J 21. revision history spansion publication number: S29JL064J_00 section description revision 01 (june 21, 2010) initial revision. revision 02 (september 1, 2010) global updated the data sheet designation from advanced information to preliminary. corrected spelling, capitalization, and grammatical errors. simultaneous read/write operations with zero latency added clarification that jl064j is only offered as a dual boot device with both top and bottom boot sectors. ordering information clarified that note 1 applies to the packing type column. device bus operation the note for the addresses column should be note 1, not note 2. reset#: hardware reset pin changed ?refer to ac characteristics on page 46? to ?refer to hardware reset (reset#) on page 47?. secured silicon region clarified the secured silicon indicator bit da ta based on factory and customer lock status. removed forward looking statements regarding factory locking features as they are supported in this device. common flash memory interface (cfi) clarified that once in the cfi query mode, the system must write the reset command to return to reading array data. enter secured silicon region/exit secured silicon region command sequence removed the incorrect generalizing statement that the secured silicon region always contains an esn. erase suspend/erase resume commands added clarification that ?it is not recommended to program the secured silicon region after an erase suspend, as proper device func tionality cannot be guaranteed.? in table 10.1, corrected the secured silicon region factory protect fourth cycle data from 81/01 to 81/ 41/01. erase and programming performance added note 5 regar ding minimum program and erase cycle endurance. pin capacitance changed section title from ?tsop pin capacitance? to ?pin capacitance?. updated values to reflect maximum capacitances for both tsop and bga. removed typical capacitance values. added specific pin clarificati ons to parameter descriptions. physical dimensions updated the vbk048 package outline drawing. revision 03 (april 7, 2011) global updated the data sheet designation from prelimi nary to full production (no designation on document). reset#: hardware reset pin added warning that keeping ce# at v il from power up through the first reset could cause erroneuous data on the first read. reset command clarified that during an embedded program or erase, if dq5 goes high then ry/by# will remain low until a reset is issued absolute maximum ratings corrected the maximum value of wp#/ acc voltage with respect to ground from +10.5v to +9.5v dc characteristics corrected voltage for autoselect and temporary sector unprotect (v id ) minimum value from 11.5v to 8.5v test conditions changed the format of the input pulse levels and input and output timing measurement reference levels to match the jl032j data sheet format hardware reset (reset#) added note to ?reset timings? figure cl arifying that ce# should only go low after reset# has gone high.
document number: 002-00856 rev. *g page 57 of 60 S29JL064J revision 04 (august 24, 2011) reset#: hardware reset pin removed warning that keeping ce# at v il from power up through the first reset could cause erroneuous data on the first read. sector erase command sequence added clarif ication regarding additional sector er ase commands during time-out period. command definitions table added note 17 to clarify additi onal sector erase commands during time-out period. hardware reset (reset#) removed note to the ?reset timings? figure clarif ying that ce# should only go low after reset# has gone high. erase and programming performance updated byte program time and word program time to 80 s. physical dimensions package drawings updated to latest version. revision 05 (december 16, 2011) global corrected all references in the text to the sector erase time-out period from 80 s to 50 s. document history page document title:S29JL064J, 64-mbit (8m 8-bit/4m 16-bit), 3 v, simultaneous read/write flash document number: 002-00856 rev. ecn no. orig. of change submission date description of change ** - rysu 06/21/2010 initial release section description
document number: 002-00856 rev. *g page 58 of 60 S29JL064J *a - rysu 09/01/2010 global updated the data sheet designation from advanced information to preliminary. corrected spelling, capitalization, and grammatical errors. simultaneous read/write operations with zero latency added clarification that jl064j is only of fered as a dual boot device with both top and bottom boot sectors. ordering information clarified that note 1 applies to the packing type column. device bus operation the note for the addresses column should be note 1, not note 2. reset#: hardware reset pin changed ?refer to ac characteristics on page 46? to ?refer to hardware reset (reset#) on page 47?. secured silicon region clarified the secured silicon indicator bi t data based on factory and customer lock status. removed forward looking statements re garding factory locking features as they are supported in this device. common flash memory interface (cfi) clarified that once in the cfi query mode, the system must write the reset command to return to reading array data. enter secured silicon region/exi t secured silicon region command sequence removed the incorrect generalizing st atement that the secured silicon region always contains an esn. erase suspend/erase resume commands added clarification that ?it is not recommended to program the secured silicon region after an erase suspend, as proper device functionality cannot be guaranteed.? in table 10.1, corrected the secured si licon region factory protect fourth cycle data from 81/01 to 81/41/01. erase and programming performance added note 5 regarding minimum program and erase cycle endurance. pin capacitance changed section title from ?tsop pin capacitance? to ?pin capacitance?. updated values to reflect maximum capacitances for both tsop and bga. removed typical capacitance values. added specific pin clarifications to parameter descriptions. physical dimensions updated the vbk048 pa ckage outline drawing. document history page (continued) document title:S29JL064J, 64-mbit (8m 8-bit/4m 16-bit), 3 v, simultaneous read/write flash document number: 002-00856 rev. ecn no. orig. of change submission date description of change
document number: 002-00856 rev. *g page 59 of 60 S29JL064J *b - rysu 04/07/2011 global updated the data sheet designation from preliminary to full production (no designation on document). reset#: hardware reset pin added warning that keeping ce# at vil fr om power up through the first reset could cause erroneuous data on the first read. reset command clarified that during an embedded progr am or erase, if dq5 goes high then ry/by# will remain low until a reset is issued absolute maximum ratings corrected the maximum value of wp#/acc voltage with respect to ground from +10.5v to +9.5v dc characteristics corrected voltage for autoselect and temporary sector unprotect (vid) minimum value from 11.5v to 8.5v test conditions changed the format of the input pulse levels and input and output timing measurement reference levels to match the jl032j data sheet format hardware reset (reset#) added note to ?reset timings? figure clarifying that ce# should only go low after reset# has gone high. *c - rysu 08/24/2011 reset#: hardware reset pin removed warning that keeping ce# at vil from power up through the first reset could cause erroneuous data on the first read. sector erase command sequence added clarification regarding additional sector erase commands during time-out period. command definitions table added note 17 to clarify additional sector erase commands during time-out period. hardware reset (reset#) removed note to the ?reset timings? figure clarifying that ce# should only go low after reset# has gone high. erase and programming performance updated byte program time and word program time to 80 s. physical dimensions package drawings updated to latest version *d - rysu 12/16/2011 globa l corrected all references in the text to the sector erase time -out period from 80 s to 50 s. *e 5038713 rysu 12/08/2015 updated to cypress template. *f 5705425 aesatmp7 04/21/2017 updated cypress logo and copyright. *g 5766160 nfb / prit 06/07/2017 updated ordering information : added ?valid combinations ? automotive grade / aec-q100?. updated operating ranges : added automotive temperature range related information. document history page (continued) document title:S29JL064J, 64-mbit (8m 8-bit/4m 16-bit), 3 v, simultaneous read/write flash document number: 002-00856 rev. ecn no. orig. of change submission date description of change
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